diff --git a/Lib/YMF262-HAL/Inc/FakeGPIO.hpp b/Lib/YMF262-HAL/Inc/FakeGPIO.hpp new file mode 100644 index 0000000..a117976 --- /dev/null +++ b/Lib/YMF262-HAL/Inc/FakeGPIO.hpp @@ -0,0 +1,19 @@ +#ifndef FAKE_GPIO_HPP +#define FAKE_GPIO_HPP + + +#include +#include "GPIO.hpp" + +struct FakeGpio { + void set_data_bus(uint8_t val){} + void set_a0(Port port){} + void set_a1(Bank address_bank){} + void set_cs(State state){} + void set_wr(State state){} + void set_ic(State state){} + void set_rd(State state){} + void delay_ticks(uint32_t n){} +}; + +#endif \ No newline at end of file diff --git a/Lib/YMF262-HAL/Inc/GPIO.hpp b/Lib/YMF262-HAL/Inc/GPIO.hpp new file mode 100644 index 0000000..cad421d --- /dev/null +++ b/Lib/YMF262-HAL/Inc/GPIO.hpp @@ -0,0 +1,20 @@ +#ifndef GPIO_HPP +#define GPIO_HPP + +enum class State{ + ACTIVE, + INACTIVE +}; + + +enum class Port{ + DATA, + ADDRESS +}; + +enum class Bank{ + BANK_0, + BANK_1, +}; + +#endif \ No newline at end of file diff --git a/Lib/YMF262-HAL/Inc/YMF262-HAL.hpp b/Lib/YMF262-HAL/Inc/YMF262-HAL.hpp index 70d5a24..6c225fd 100644 --- a/Lib/YMF262-HAL/Inc/YMF262-HAL.hpp +++ b/Lib/YMF262-HAL/Inc/YMF262-HAL.hpp @@ -2,11 +2,13 @@ #define YMF262_HAL_HPP #include +#include "GPIO.hpp" template class YMF262_HAL{ private: - GPIOPolicy _gpio; + + GPIOPolicy _gpio; uint32_t _t_icw_ticks; uint32_t _t_as_ticks; uint32_t _t_ah_ticks; @@ -19,6 +21,21 @@ class YMF262_HAL{ uint32_t _t_acc_ticks; uint32_t _t_rdh_ticks; uint32_t _t_recovery_ticks; + + void write_bus(Bank bank, Port port, uint8_t data){ + _gpio.set_a0(port); + _gpio.set_a1(bank); + _gpio.delay_ticks(_t_as_ticks); + _gpio.set_cs(State::ACTIVE); + _gpio.set_wr(State::ACTIVE); + _gpio.set_data_bus(data); + _gpio.delay_ticks(_t_wds_ticks); + _gpio.set_wr(State::INACTIVE); + _gpio.set_cs(State::INACTIVE); + _gpio.delay_ticks(_t_wdh_ticks); + _gpio.delay_ticks(_t_recovery_ticks); + + }; public: @@ -38,6 +55,12 @@ class YMF262_HAL{ _t_acc_ticks = (uint32_t)(150 * ticks_per_ns); _t_rdh_ticks = (uint32_t)(10 * ticks_per_ns); }; + + void write(Bank bank, uint8_t reg, uint8_t data){ + write_bus(bank,Port::ADDRESS,reg); + write_bus(bank,Port::DATA,data); + }; + }; #endif \ No newline at end of file