diff --git a/Tests/FakeGPIO.hpp b/Tests/FakeGPIO.hpp index 77d1871..b85dd9a 100644 --- a/Tests/FakeGPIO.hpp +++ b/Tests/FakeGPIO.hpp @@ -7,16 +7,37 @@ #include "GPIO.hpp" struct FakeGpio { - std::vector log; + std::vector operations; + std::vector bus_values; + std::vector delays; - void set_data_bus(uint8_t val) { log.push_back("data " + std::to_string(val)); } - void set_a0(Port port) { log.push_back(port == Port::ADDRESS ? "a0 ADDR" : "a0 DATA"); } - void set_a1(Bank bank) { log.push_back(bank == Bank::BANK_0 ? "a1 B0" : "a1 B1"); } - void set_cs(State s) { log.push_back(s == State::ACTIVE ? "cs ON" : "cs OFF"); } - void set_wr(State s) { log.push_back(s == State::ACTIVE ? "wr ON" : "wr OFF"); } - void set_ic(State s) { log.push_back(s == State::ACTIVE ? "ic ON" : "ic OFF"); } - void set_rd(State s) { log.push_back(s == State::ACTIVE ? "rd ON" : "rd OFF"); } - void delay_ticks(uint32_t n) { log.push_back("delay " + std::to_string(n)); } + + void set_data_bus(uint8_t val) { + operations.push_back("data_bus"); + bus_values.push_back(val); + } + void set_a0(Port port) { + operations.push_back(port == Port::ADDRESS ? "a0 ADDRESS" : "a0 DATA"); + } + void set_a1(Bank bank) { + operations.push_back(bank == Bank::BANK_0 ? "a1 BANK_0" : "a1 BANK_1"); + } + void set_cs(State s) { + operations.push_back(s == State::ACTIVE ? "cs ACTIVE" : "cs INACTIVE"); + } + void set_wr(State s) { + operations.push_back(s == State::ACTIVE ? "wr ACTIVE" : "wr INACTIVE"); + } + void set_ic(State s) { + operations.push_back(s == State::ACTIVE ? "ic ACTIVE" : "ic INACTIVE"); + } + void set_rd(State s) { + operations.push_back(s == State::ACTIVE ? "rd ACTIVE" : "rd INACTIVE"); + } + void delay_ticks(uint32_t n) { + operations.push_back("delay_ticks"); + delays.push_back(n); + } }; #endif \ No newline at end of file diff --git a/Tests/test_write.cpp b/Tests/test_write.cpp index 5c69a13..f706a54 100644 --- a/Tests/test_write.cpp +++ b/Tests/test_write.cpp @@ -2,18 +2,22 @@ #include "YMF262-HAL.hpp" #include "FakeGPIO.hpp" -TEST(YMF262Write, FazDoisCiclos) { +class YMF262_HALWriteTest : public ::testing::Test { +protected: FakeGpio fake; - YMF262_HAL hal(fake, 14318000, 216000000); + YMF262_HAL hal{fake, 14318000, 216000000}; + // ^ fake e hal criados ANTES de cada teste, prontos pra usar +}; +TEST_F(YMF262_HALWriteTest,TestForEmptyRun) { hal.write(Bank::BANK_0, 0x40, 0x20); + EXPECT_NE(fake.operations.size(),0); + EXPECT_NE(fake.bus_values.size(), 0); + EXPECT_NE(fake.delays.size(), 0); - // imprime o que foi registrado (pra você VER a coreografia) - for (const auto& linha : fake.log) { - std::cout << linha << "\n"; - } +} - // verificações básicas: o primeiro ciclo é endereço, o barramento recebeu 0x40 (64) - EXPECT_EQ(fake.log.front(), "a0 ADDR"); // começou em modo endereço - EXPECT_FALSE(fake.log.empty()); // anotou algo +TEST_F(YMF262_HALWriteTest, A0MudaEntreCiclos) { + hal.write(Bank::BANK_0, 0x40, 0x20); + EXPECT_EQ(fake.operations.front(), "a0 ADDRESS"); } \ No newline at end of file