Configure YMF262 parallel bus GPIO and fix PLL settings

Browse Source

Add D0-D7 data bus (GPIOC), control signals _WR/_RD/_CS/_IC and
  address lines A0/A1 (GPIOF), and _IRQ input for the YMF262 interface.
  Fix PLL parameters (PLLM=8, PLLN=432, PLLQ=12) for correct 216 MHz
  operation from the 8 MHz HSE, and switch USB 48 MHz clock to PLLSAI.

...

This commit is contained in:

Gustavo Henrique Santos Souza de Miranda

2026-04-29 01:43:00 -03:00

parent bf6cec40d1

commit 297cf1a201

5 changed files with 302 additions and 82 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download Patch File Download Diff File Expand all files Collapse all files

.mxproject

+8 -8

File diff suppressed because one or more lines are too long