Files
YMF262_devboard_Firmware/.mxproject
T
Gustavo Henrique Santos Souza de Miranda 297cf1a201 Configure YMF262 parallel bus GPIO and fix PLL settings
Add D0-D7 data bus (GPIOC), control signals _WR/_RD/_CS/_IC and
  address lines A0/A1 (GPIOF), and _IRQ input for the YMF262 interface.
  Fix PLL parameters (PLLM=8, PLLN=432, PLLQ=12) for correct 216 MHz
  operation from the 8 MHz HSE, and switch USB 48 MHz clock to PLLSAI.
2026-04-29 01:43:00 -03:00

26 lines
8.6 KiB
Plaintext

[PreviousLibFiles]
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